ICM-20690
12.61 REGISTER 95 – FSYNC ODR DELAY COUNTER HIGH BYTE
Register Name: ODR_DLY_CNT_HI
Register Type: READ/WRITE
Register Address: 95 (Decimal); 5F (Hex)
BIT
NAME
FUNCTION
[7:0]
ODR_DLY_TIME_CNT[15:8]
High byte of FSYNC ODR delay counter.
12.62 REGISTER 96 – FSYNC ODR DELAY COUNTER LOW BYTE
Register Name: ODR_DLY_CNT_LO
Register Type: READ/WRITE
Register Address: 96 (Decimal); 60 (Hex)
BIT
NAME
FUNCTION
[7:0]
ODR_DLY_TIME_CNT[7:0] Low byte of FSYNC ODR delay counter.
12.63 REGISTER 97 – FIFO WATERMARK THRESHOLD IN NUMBER OF BYTES
Register Name: FIFO_WM_TH
Register Type: READ/WRITE
Register Address: 97 (Decimal); 61 (Hex)
BIT
NAME
FUNCTION
[7:0]
FIFO_WM_TH
FIFO watermark threshold in number of bytes. If zero then watermark
interrupt is disabled.
12.64 REGISTER 99 – SLAVE 0 DATA OUT
Register Name: I2C_SLV0_DO
Register Type: READ/WRITE
Register Address: 99 (Decimal); 63 (Hex)
BIT
[7:0]
NAME
I2C_SLV0_DO
FUNCTION
Data out when slave 0 is set to write.
12.65 REGISTER 100 – SLAVE 1 DATA OUT
Register Name: I2C_SLV1_DO
Register Type: READ/WRITE
Register Address: 100 (Decimal); 64 (Hex)
BIT
NAME
FUNCTION
[7:0]
I2C_SLV1_DO
Data out when slave 1 is set to write.
Page 63 of 76
Document Number: DS-000178
Revision: 1.0
TDK [ TDK ELECTRONICS ]
