ICM-20690
BIT
NAME
FUNCTION
1 – Enable the I2C master interface module: Pins AUX_DA and AUX_CL are
isolated from pins AP_SDA/AP_SDI and AP_SCL/AP_SCLK.
0 – Disable the I2C master interface module: Pins AUX_DA and AUX_CL are
driven by pins AP_SDA/AP_SDI and AP_SCL/AP_SCLK.
Disable I2C slave interface to host and put the interface in SPI mode.
Reserved
[5]
I2C_MST_EN
[4]
[3]
I2C_IF_DIS
-
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one
clock cycle of the internal 20MHz clock.
Reserved
[2]
[1]
FIFO_RST
-
1 – Reset gyroscope digital signal path, accelerometer digital signal path, and
temperature sensor digital signal path. This bit also clears all the sensor
registers.
[0]
SIG_COND_RST
12.71 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
[7]
[6]
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit
automatically clears to 0 once the reset is done.
When set to 1, the chip is set to sleep mode.
DEVICE_RESET
SLEEP
When set to 1, and SLEEP and GYRO_STANDBY are not set to 1, the chip will
cycle between sleep and taking a single accelerometer sample at a rate
determined by SMPLRT_DIV.
NOTE: When all accelerometer axes are disabled via PWR_MGMT_2 register
bits and cycle is enabled, the chip will wake up at the rate determined by the
respective registers above, but will not take any samples.
When set, the gyro drive and PLL circuitry are enabled, but the sense paths are
disabled. This is a low power mode that allows quick enabling of the gyros.
When set to 1, this bit disables the temperature sensor.
Code Clock Source
[5]
CYCLE
[4]
[3]
GYRO_STANDBY
TEMP_DIS
0
1
Internal 20 MHz oscillator
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
2
3
4
5
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
[2:0]
CLKSEL[2:0]
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
6
7
Internal 20MHz oscillator
Stops the clock and keeps timing generator in reset
Page 66 of 76
Document Number: DS-000178
Revision: 1.0
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