ICM-20690
FCHOICE_OIS_B
FCHOICE_B
DLPF_CFG
Filter BW (Hz) Filter Delay (ms)
ODR (kHz)
32
11
10
10
01
00
00
00
00
00
00
xx
10
00
00
00
00
00
00
00
00
x
x
x
8800
3600
3600
250
184
92
0.064
0.11
0.17
0.97
2.9
32
8
8
x
1
2
3
4
5
6
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
3.9
41
5.9
20
9.9
10
5
17.85
33.48
12.69 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
NAME
FUNCTION
[7]
ACCEL_INTEL_EN
This bit enables the Wake-on-Motion detection logic.
0 – Do not use.
1 – Compare the current sample with the previous sample,
[6]
ACCEL_INTEL_MODE
Used for OIS path accelerometer DLPF configuration as shown in the table
below.
Reserved
[5:4]
[3:1]
ACCEL_FCHOICE_OIS_B
-
0 – Set WoM interrupt on the OR of all enabled accelerometer thresholds.
1 – Set WoM interrupt on the AND of all enabled accelerometer threshold.
Default setting is 0
[0]
WOM_INT_MODE
ACCEL_FCHOICE_OIS_B ACCEL_FCHOICE_B A_DLPF_CFG
Filter BW (Hz)
Filter Delay (ms)
ODR (kHz)
11
10
01
01
01
01
01
01
01
X
0
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
1046.00
420.00
218.10
218.10
99.00
44.80
21.20
10.20
5.05
0.50
1.38
1.88
1.88
2.88
4.88
8.87
16.80
32.50
4
1
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
12.70 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
NAME
FUNCTION
[7]
-
Reserved
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
[6]
FIFO_EN
Page 65 of 76
Document Number: DS-000178
Revision: 1.0
TDK [ TDK ELECTRONICS ]
