ICM-20602
9.15 REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
NAME
FUNCTION
Divides the internal sample rate (see register CONFIG) to generate the
sample rate that controls sensor data output rate, FIFO sample rate.
NOTE: This ꢂegisteꢂ is oꢁlꢑ effeꢃtiꢄe ꢊheꢁ FCHOICE_B ꢂegisteꢂ ꢎits aꢂe ꢈꢋꢎꢆꢆ, aꢁd
(0 < DLPF_CFG < 7).
[7:0]
SMPLRT_DIV[7:0]
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1 kHz
9.16 REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
NAME
FUNCTION
-
FIFO_MODE
Default configuration value is 1. User should set it to 0.
Wheꢁ set to ꢖꢍꢋ, ꢊheꢁ the FIFO is full, additioꢁal ꢊꢂites ꢊill ꢁot ꢎe
written to FIFO.
[6]
Wheꢁ set to ꢖꢆꢋ, ꢊheꢁ the FIFO is full, additioꢁal ꢊꢂites ꢊill ꢎe ꢊꢂitteꢁ
to the FIFO, replacing the oldest data.
Enables the FSYNC pin data to be sampled.
[5:3]
EXT_SYNC_SET[2:0]
EXT_SYNC_SET
FSYNC bit location
function disabled
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
ACCEL_XOUT_L[0]
ACCEL_YOUT_L[0]
ACCEL_ZOUT_L[0]
0
1
2
3
4
5
6
7
FSYNC will be latched to capture short strobes. This will be done such
that if F“YNC toggles, the latꢃhed ꢄalue toggles, ꢎut ꢊoꢁꢋt toggle agaiꢁ
until the new latched value is captured by the sample rate strobe.
Foꢂ the DLPF to ꢎe used, FCHOICE_B[ꢍ:ꢆ] is ꢈꢋꢎꢆꢆ.
[2:0]
DLPF_CFG[2:0]
See the table below.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [ꢍ:ꢆ] = ꢈꢎꢋꢆꢆ. The gꢑꢂosꢃope aꢁd teꢌpeꢂatuꢂe seꢁsoꢂ aꢂe filteꢂed
according to the value of DLPF_CFG and FCHOICE_B as shown in the table below.
Document Number: DS-000176
Page 36 of 57
Revision: 1.0
Revision Date: 10/03/2016
TDK [ TDK ELECTRONICS ]
