SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: IICS2
Address: FDH
7
-
6
-
5
-
4
-
3
2
1
0
BF
Reset
00H
AB_EN
BF_EN AB_F
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration
lost condition. Set this bit when multi-master and slave connection. Clear this bit when
single master to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear
this bit will always generate a start condition to bus when MStart is set. Set this bit when
multi-master and slave connection. Clear this bit when single master to single slave.
AB_F: Arbitration lost bit. (Master mode only)
In multi-master condition, when send out data bit “1” but return back “0”, bus arbitration
lost occurred and this bit will be set. Software need to clear this bit and check until BF=0
to resend data again.
BF: Bus busy bit. (Master mode only)
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop and a period
passed(about 4.7us), this bit will be cleared. This bit can be cleared by software to
return ready state.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
63
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
