SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
Mnemonic: SPIC1
Address: F1h
7
6
5
4
3
2
1
0
Reset
SPIEN SPIMSS SPISSP SPICKP SPICKE
SPIBR[2:0]
08h
SPIEN: Enable SPI module. “1” is Enable. “0” is Disable.
SPIMSS: Master or Slave mode Select
“1” is Master mode.
“0” is Slave mode.
SPISSP: Slave Select (SS) active polarity (slave mode used only)
“1” - high active.
“0” - low active.
SPICKP: Clock idle polarity (master mode used only)
“1” – SCK high during idle. Ex :
“0” - SCK low during idle. Ex :
SPICKE: Clock sample edge select.
“1” – data latch in rising edge
“0” – data latch in falling edge.
* To ensure the data latch stability, SM59R16A5 generate the output data as given in the following
example, the other side can latch the stable data no matter in rising or falling edge.
sufficient set-up time
sufficient hold time
SPIBR[2:0]: SPI baud rate select (master mode used only), here Fosc is the external crystal or oscillator
frequency :
SPIBR[2:0] Baud rate
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
Fosc/128
Fosc/256
Fosc/512
Mnemonic: SPIC2
Address: F2h
7
6
5
4
3
-
2
1
0
Reset
00h
SPIFD
TBC[2:0]
RBC[2:0]
SPIFD: Full-duplex mode enable.
“1” : enable full-duplex mode.
“0” : disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero, i.e., only 8-bit
communication is allowed in the full-duplex mode. When the master device transmits data to the
slave device via the MOSI line, the slave device responds sends data back to the master device
via the MISO line. This implies that full-duplex transmission with both out-data and in-data are
synchronized with the same clock SCK as shown below.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
65
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
