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SM59R05A5L25 参数 Datasheet PDF下载

SM59R05A5L25图片预览
型号: SM59R05A5L25
PDF下载: 下载PDF文件 查看货源
内容描述: SM59R16A5 / SM59R09A5 / SM59R05A5\n8位微控制器\n64KB / 36KB / 20KB具有ISP功能的Flash\n和2KB RAM的嵌入式 [SM59R16A5/SM59R09A5/SM59R05A5 8-Bit Micro-controller 64KB/36KB/20KB with ISP Flash & 2KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 89 页 / 3025 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59R16A5/SM59R09A5/SM59R05A5  
8-Bit Micro-controller  
64KB/36KB/20KB with ISP Flash  
& 2KB RAM embedded  
Slave mode:  
IICA1[7:1]: IIC Address registers  
This is the first 7-bit address for this slave module. It will be checked when an address (from  
master) is received  
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by  
hardware. When IIC bus gets or send first data, this bit will clear automatically.  
Master mode:  
IICA1[7:1]: IIC Address registers  
This 7-bit address indicate the slave with which it want to communicate.  
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It  
appears at the 8th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the  
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the  
module is in master transmit mode.  
Fig. 14-2: RW bit in the 8th bit after IIC address  
Address: FBh  
Mnemonic: IICA2  
7
6
5
4
3
2
1
0
Reset  
60h  
IICA2[7:1]  
R/W  
Match2 or RW2  
R or R/W  
Slave mode:  
IICA2[7:1]: IIC Address registers  
This is the second 7-bit address for this slave module.  
It will be checked when an address (from master) is received  
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by  
hardware. When IIC bus gets or send first data, this bit will clear automatically.  
Master mode:  
IICA2[7:1]: IIC Address registers  
This 7-bit address indicate the slave with which it want to communicate.  
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is  
used to tell the salve the direction of the following communication. If it is 1, the module is in  
master receive mode. If 0, the module is in master transmit mode.  
Mnemonic: IICRWD  
Address: FCh  
7
6
5
4
3
2
1
0
Reset  
00h  
IICRWD[7:0]  
IICRWD[7:0]: IIC read write data buffer.  
In receiving (read) mode, the received byte is stored here.  
In transmitting mode, the byte to be shifted out through SDA stays here.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M047  
62  
Ver.G SM59R16A5 01/2014  
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