SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
MISO
MISO
Input Shift register
SPIRXD
Output Shift register
SPITXD
MOSI
SCK
MOSI
SCK
Output Shift register
SPITXD
Input Shift register
SPIRXD
Clock Generator
SyncMos Slave
SyncMos Master
TBC[2:0]: SPI transmitter bit counter, here 1-8 bits are allowed except for the full-duplex mode
TBC[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Bit counter
8 bits output
1 bit output
2 bits output
3 bits output
4 bits output
5 bits output
6 bits output
7 bits output
RBC[2:0]: SPI receiver bit counter, here 1-8 bits are allowed except for the full-duplex mode
RBC[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Bit counter
8 bits input
1 bit input
2 bits input
3 bits input
4 bits input
5 bits input
6 bits input
7 bits input
Mnemonic: SPIS
Address: F5h
7
-
6
5
4
3
2
1
0
Reset
40h
SPIMLS SPIOV SPITXIF SPITDR SPIRXIF SPIRDR SPIRS
SPIMLS: MSB or LSB output /input first
“1” : MSB output/input first
“0” : LSB output/input first
SPIOV: Overflow flag.
When SPIRDR is set (one byte in SPIRXD but has not been taken away) and the next data also
enters (there is no blocking function), this flag will be set to inform that the received data in
SPIRXD is damaged by this overflow. It is clear by hardware when SPIRDR is cleared.
SPITXIF: Transmit Interrupt Flag.
This bit is set when the data of the SPITXD register is downloaded to the shift register.
SPITDR: Transmit Data Ready.
When MCU finish writing data to SPITXD register, the MCU needs to set this bit to ‘1’ to inform the
SPI module to send the data. After SPI module finishes sending the data from SPITXD or SPITXD
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
66
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
