SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
is downloaded to shift register, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
This bit is set after the SPIRXD is loaded with a newly receive data.
SPIRDR: Receive Data Ready.
When a byte is received, SPIRDR is set as a flag to inform MCU. The MCU must clear this bit
after it gets the data from SPIRXD register. If the SPI module on the transmit side writes new
data into the SPIRXD before this bit is cleared, then the data will be overwritten.
SPIRS: Receive Start.
This bit set to “1” to inform the SPI module to receive the data into SPIRXD register.
Mnemonic: SPITXD
Address: F3h
0 Reset
7
6
5
4
3
2
1
SPITXD[7:0]
00h
SPITXD[7:0]: Transmit data buffer.
Mnemonic: SPIRXD
Address: F4h
7
6
5
4
3
2
1
0
Reset
00h
SPIRXD[7:0]
SPIRXD[7:0]: Receive data buffer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047 67 Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
