SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
15. SPI function
Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with
slave devices.
The interrupt vector is 4Bh.
There are 4 signals used in SPI, they are
SPI_MOSI: data output in the master mode, data input in the slave mode,
SPI_MISO: data input in the master mode, data output in the slave mode,
SPI_SCK: clock output form the master, the above data are synchronous to this signal
SPI_SS: input in the slave mode.
This slave device detects this signal to judge if it is selected by the master.
In the master mode, it can select the desired slave device by any IO with value = 0. Fig. 15-1 is an example showing the
relation of the 4 signals between master and slaves.
Slave 2
Master
Slave 1
MOSI
MISO
CLK
MOSI
MISO
CLK
MOSI
MISO
CLK
IO
IO
SS
SS
Fig. 15-1: SPI signals between master and slave devices
There is only one channel SPI interface. The SPI SFRs are shown as below:
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
SPI function
P4UR
1
P2PW
M
AUX
Auxiliary register
91h
F1h
BRGS
-
P4SPI
P4IIC
P0KBI
DPS
00H
08H
SPI control register
1
SPI control register
2
SPI status register
SPI transmit data
buffer
SPISS
P
SPIC1
SPIEN SPIMSS
SPIFD
SPICKP SPICKE
-
SPIBR[2:0]
RBC[2:0]
SPIC2
SPIS
F2h
F5h
F3h
TBC[2:0]
00H
40H
00H
-
SPIMLS SPIOV SPITXIF SPITDR SPIRXIF SPIRDR SPIRS
SPITXD[7:0]
SPITXD
SPI receive data
buffer
SPIRXD
F4h
SPIRXD[7:0]
00H
Mnemonic: AUX
Address: 91h
7
6
-
5
4
3
2
1
0
DPS
Reset
00H
BRGS
P4SPI
P4UR1
P4IIC
P0KBI
P2PWM
P4SPI: P4SPI = 0 – SPI function on P1.
P4SPI = 1 – SPI function on P4.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047 64 Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
