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UPSD3412C-24U6T 参数 Datasheet PDF下载

UPSD3412C-24U6T图片预览
型号: UPSD3412C-24U6T
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存可编程系统设备与8032单片机内核和16Kbit的SRAM [Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM]
分类和应用: 闪存静态存储器微控制器
文件页数/大小: 152 页 / 1492 K
品牌: STMICROELECTRONICS [ ST ]
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UPSD3212C, UPSD3212CV  
Table 44. Description of the SCON Bits  
Bit  
Symbol  
Function  
(SM1,SM0)=(0,0): Shift Register. Baud rate = f /12  
OSC  
7
SM0  
(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable  
(SM1,SM0)=(0,1): 8-bit UART. Baud rate = f /64 or f  
(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable  
/32  
OSC  
OSC  
6
SM1  
Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if  
SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode  
1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2  
should be '0'  
5
SM2  
Enables serial reception. Set by software to enable reception. Clear by software to  
disable reception  
4
3
2
REN  
TB8  
RB8  
The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as  
desired  
In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if  
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used  
Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or at  
the beginning of the Stop Bit in the other modes, in any serial transmission. Must be  
cleared by software  
1
0
TI  
Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or  
halfway through the Stop Bit in the other modes, in any serial reception (except for  
SM2). Must be cleared by software  
RI  
60/152  
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