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UPSD3412C-24U6T 参数 Datasheet PDF下载

UPSD3412C-24U6T图片预览
型号: UPSD3412C-24U6T
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存可编程系统设备与8032单片机内核和16Kbit的SRAM [Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM]
分类和应用: 闪存静态存储器微控制器
文件页数/大小: 152 页 / 1492 K
品牌: STMICROELECTRONICS [ ST ]
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UPSD3212C, UPSD3212CV  
Mode 3. Timer 1 in Mode 3 simply holds its count.  
The effect is the same as setting TR1 = 0.  
Mode 3 is provided for applications requiring an  
extra 8-bit timer on the counter. With Timer 0 in  
Mode 3, an uPSD321X Devices can look like it has  
three Timer/Counters. When Timer 0 is in Mode 3,  
Timer 1 can be turned on and off by switching it out  
of and into its own Mode 3, or can still be used by  
the serial port as a baud rate generator, or in fact,  
in any application not requiring an interrupt.  
Timer 0 in Mode 3 establishes TL0 and TH0 as two  
separate counters. The logic for Mode 3 on Timer  
0 is shown in Figure 26. TL0 uses the Timer 0 con-  
trol Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is  
locked into a timer function (counting machine cy-  
cles) and takes over the use of TR1 and TF1 from  
Timer 1. Thus, TH0 now controls the “Timer 1“ In-  
terrupt.  
Figure 26. Timer/Counter Mode 3: Two 8-bit Counters  
f
÷ 12  
OSC  
C/T = 0  
C/T = 1  
TL0  
(8 bits)  
TF0  
Interrupt  
T0 pin  
Control  
TR0  
Gate  
INT0 pin  
TH1  
(8 bits)  
f
TF1  
Interrupt  
÷ 12  
OSC  
Control  
TR1  
AI06624  
57/152  
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