UPSD3212C, UPSD3212CV
Figure 72. Input Macrocell Timing (product term clock)
t
t
INL
INH
PT CLOCK
INPUT
t
t
IH
IS
OUTPUT
t
INO
AI03101
Table 104. Input Macrocell Timing (5V Devices)
PT
Aloc
Turbo
Off
Symbol
Parameter
Input Setup Time
Conditions
Min
Max
Unit
t
0
15
9
ns
ns
ns
ns
ns
IS
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
t
t
t
t
Input Hold Time
+ 10
IH
NIB Input High Time
NIB Input Low Time
INH
INL
INO
9
NIB Input to Combinatorial Delay
34
+ 2
+ 10
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t
and t
.
LXAX
AVLX
Table 105. Input Macrocell Timing (3V Devices)
PT
Aloc
Turbo
Off
Symbol
Parameter
Input Setup Time
Conditions
Min
Max
Unit
t
0
ns
ns
ns
ns
ns
IS
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
t
t
t
t
Input Hold Time
25
12
12
+ 20
IH
NIB Input High Time
NIB Input Low Time
INH
INL
INO
NIB Input to Combinatorial Delay
46
+ 4
+ 20
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
and t
.
LXAX
AVLX
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STMICROELECTRONICS [ ST ]
