UPSD3212C, UPSD3212CV
Figure 70. Asynchronous RESET / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 71. Asynchronous Clock Mode Timing (product term clock)
tCHA
tCLA
CLOCK
INPUT
tSA
tHA
tCOA
REGISTERED
OUTPUT
AI02859
Table 102. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
PT
Turbo Slew
Symbol
Parameter
Conditions
Min
Max
38.4
62.5
71.4
Unit
MHz
MHz
MHz
Aloc
Off
Rate
Maximum Frequency
External Feedback
1/(t +t
)
SA COA
Maximum Frequency
f
1/(t +t
–10)
)
MAXA
SA COA
Internal Feedback (f
)
CNTA
Maximum Frequency
Pipelined Data
1/(t
+t
CHA CLA
t
t
t
t
t
t
t
Input Setup Time
7
8
9
9
+ 2
+ 10
ns
ns
ns
ns
ns
ns
ns
SA
Input Hold Time
HA
Clock Input High Time
Clock Input Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
+ 10
+ 10
+ 10
CHA
CLA
COA
ARDA
MINA
21
11
– 2
Any macrocell
+ 2
1/f
CNTA
16
136/152
STMICROELECTRONICS [ ST ]
