UPSD3212C, UPSD3212CV
Table 101. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
Slew
PT
Aloc
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
22.2
28.5
40.0
Unit
MHz
MHz
MHz
(1)
rate
Maximum Frequency
External Feedback
1/(t +t
)
CO
S
Maximum Frequency
f
1/(t +t –10)
S CO
MAX
Internal Feedback (f
)
CNT
Maximum Frequency
Pipelined Data
1/(t +t
)
CH CL
t
t
t
t
t
Input Setup Time
Input Hold Time
20
0
+ 4
+ 20
ns
ns
ns
ns
ns
S
H
Clock High Time
Clock Low Time
Clock to Output Delay
Clock Input
Clock Input
Clock Input
15
10
CH
CL
CO
25
25
– 6
Any
macrocell
t
t
CPLD Array Delay
+ 4
ns
ns
ARD
(2)
t +t
CH CL
25
MIN
Minimum Clock Period
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t = t + t
.
CL
CLCL
CH
135/152
STMICROELECTRONICS [ ST ]
