UPSD3212C, UPSD3212CV
Table 103. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
PT
Aloc
Turbo Slew
Symbol
Parameter
Conditions
1/(t +t
Min
Max
21.7
27.8
33.3
Unit
MHz
MHz
MHz
Off
Rate
Maximum Frequency
External Feedback
)
SA COA
Maximum Frequency
f
1/(t +t
–10)
)
MAXA
SA COA
Internal Feedback (f
)
CNTA
Maximum Frequency
Pipelined Data
1/(t
+t
CHA CLA
t
t
t
t
t
t
t
Input Setup Time
Input Hold Time
10
12
17
13
+ 4
+ 20
ns
ns
ns
ns
ns
ns
ns
SA
HA
Clock High Time
+ 20
+ 20
+ 20
CHA
CLA
COA
ARD
MINA
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
36
25
– 6
Any macrocell
+ 4
1/f
CNTA
36
137/152