UPSD3212C, UPSD3212CV
Figure 68. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 98. CPLD Combinatorial Timing (5V Devices)
Slew
PT
Aloc
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
20
Unit
ns
(1)
rate
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
(2)
+ 2
+ 10
+ 10
+ 10
+ 10
+ 10
– 2
t
PD
CPLD Input to CPLD Output
Enable
t
t
t
t
t
21
– 2
– 2
– 2
ns
EA
CPLD Input to CPLD Output
Disable
21
ns
ER
CPLD Register Clear or Preset
Delay
21
ns
ARP
ARPW
ARD
CPLD Register Clear or Preset
Pulse Width
10
ns
Any
macrocell
CPLD Array Delay
11
+ 2
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
PD
output (80-pin package only)
Table 99. CPLD Combinatorial Timing (3V Devices)
Slew
PT
Aloc
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
40
Unit
ns
(1)
rate
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
(2)
+ 4
+ 20
+ 20
+ 20
+ 20
+ 20
– 6
t
PD
CPLD Input to CPLD Output
Enable
t
t
t
t
t
43
– 6
– 6
– 6
ns
EA
CPLD Input to CPLD Output
Disable
43
ns
ER
CPLD Register Clear or
Preset Delay
40
ns
ARP
ARPW
ARD
CPLD Register Clear or
Preset Pulse Width
25
ns
Any
macrocell
CPLD Array Delay
25
+ 4
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
PD
output (80-pin package only)
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STMICROELECTRONICS [ ST ]
