UPSD3212C, UPSD3212CV
Table 80. Power Management Mode Registers PMMR2
Bit 0
Bit 1
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
0 = on WR input to the PLD AND Array is connected.
PLD Array
WR
Bit 2
Bit 3
Bit 4
Bit 5
1 = off WR input to PLD AND Array is disconnected, saving power.
0 = on RD input to the PLD AND Array is connected.
PLD Array
RD
1 = off RD input to PLD AND Array is disconnected, saving power.
0 = on PSEN input to the PLD AND Array is connected.
1 = off PSEN input to PLD AND Array is disconnected, saving power.
0 = on ALE input to the PLD AND Array is connected.
PLD Array
PSEN
PLD Array
ALE
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6
Bit 7
X
X
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.
Table 81. APD Counter Operation
APD Enable Bit
ALE Level
X
APD Counter
0
1
1
Not Counting
Not Counting
Pulsing
0 or 1
Counting (Generates PDN after 15 Clocks)
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STMICROELECTRONICS [ ST ]
