Memory and register map
STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5349 to
0x00 53DF
Reserved area (153 byte)
ADC data buffer registers
Reserved area (12 byte)
0x00 5354 to
0x00 53FF
ADC1
ADC_DBxR
0x00
0x00 5354 to
0x00 53FF
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
0x00 5408
0x00 5409
0x00 540A
0x00 540B
0x00 540C
0x00 540D
0x00 540E
0x00 540F
ADC _CSR
ADC_CR1
ADC control/status register
ADC configuration register 1
0x00
0x00
0x00
0x00
0xXX
0xXX
0x00
0x00
0x03
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
ADC_CR2
ADC configuration register 2
ADC_CR3
ADC configuration register 3
ADC_DRH
ADC data register high
ADC_DRL
ADC data register low
ADC_TDRH
ADC_TDRL
ADC_HTRH
ADC_HTRL
ADC_LTRH
ADC_LTRL
ADC_AWSRH
ADC_AWSRL
ADC_AWCRH
ADC_AWCRL
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
ADC low threshold register low
ADC analog watchdog status register high
ADC analog watchdog status register low
ADC analog watchdog control register high
ADC analog watchdog control register low
ADC1
0x00 5410 to
0x00 57FF
Reserved area (1008 byte)
1. Depends on the previous reset source.
2. Write only register.
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