STM8S003F3 STM8S003K3
Memory and register map
Table 10. CPU/SWIM/debug module/interrupt controller registers
Reset
Status
Address
Block
Register Label
Register Name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 byte)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F78 to
0x00 7F79
Reserved area (2 byte)
SWIM control status register
Reserved area (15 byte)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81 to
0x00 7F8F
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