Memory and register map
STM8S003F3 STM8S003K3
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 50CC
0x00 50CD
CLK_HSITRIMR
CLK_SWIMCCR
HSI clock calibration trimming register
SWIM clock control register
0x00
CLK
0bXXXX
XXX0
0x00 50CE to
0x00 50D0
Reserved area (3 byte)
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x00 50D3 to
0x00 50DF
Reserved area (13 byte)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX(2)
0x00
IWDG
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 byte)
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
0x00
0x3F
0x00
0x1F
AWU
BEEP
0x00 50F4 to
0x00 50FF
Reserved area (12 byte)
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x07
0xFF
0xFF
SPI_ICR
SPI_SR
SPI
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
0x00 5208 to
0x00 520F
Reserved area (8 byte)
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
I2C frequency register
I2C own address register low
I2C own address register high
Reserved
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C
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DocID018576 Rev 5
STMICROELECTRONICS [ ST ]
