Option bytes
STM8S003F3 STM8S003K3
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
Read-out
0x4800
protection
(ROP)
OPT0
ROP[7:0]
UBC[7:0]
0x00
0x4801
0x4802
OPT1
0x00
0xFF
User boot code
(UBC)
NOPT1
NUBC[7:0]
Alternate
function
remapping
(AFR)
Reserve
0x4803
0x4804
0x4805
OPT2
NOPT2
OPT3
AFR7
AFR6
NAFR6
AFR5
AFR3
AFR2
AFR1
AFR0
0x00
0xFF
0x00
d
NAFR7
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
LSI
_EN
IWDG
_HW
WWDG
_HW
WWDG
_HALT
Reserved
HSITRIM
Misc. option
Clock option
NHSI
TRIM
NLSI
_EN
NIWDG NWWDG NWWDG
0x4806
0x4807
0x4808
NOPT3
OPT4
Reserved
0xFF
0x00
0xFF
_HW
_HW
_HALT
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
Reserved
NEXT
CLK
NCKAW
USEL
NPR
SC1
NPR
SC0
NOPT4
Reserved
0x4809
0x480A
OPT5
HSECNT[7:0]
NHSECNT[7:0]
0x00
0xFF
HSE clock
startup
NOPT5
Table 13. Option byte description
Description
Option byte no.
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT0
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