STM8S003F3 STM8S003K3
Interrupt vector mapping
7
Interrupt vector mapping
Table 11. Interrupt mapping
Wakeup from Wakeup from
IRQ
no.
Source
block
Description
Vector address
Halt mode
Active-halt mode
-
-
RESET
TRAP
TLI
Reset
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
Software interrupt
0
1
2
3
4
5
6
7
8
9
10
External top level interrupt
Auto wake up from halt
Clock controller
-
-
AWU
CLK
-
Yes
-
-
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
-
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Yes(1)
Yes
Yes
Yes
Yes
Yes(1)
Yes
Yes
Yes
Yes
Reserved
Reserved
-
SPI
End of transfer
Yes
-
Yes
-
TIM1 update/overflow/underflow/
trigger/break
11
TIM1
0x00 8034
12
13
14
15
16
17
18
19
20
21
TIM1
TIM1 capture/compare
TIM2 update /overflow
TIM2 capture/compare
-
-
-
-
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
TIM2
TIM2
-
Reserved
-
Reserved
UART1
Tx complete
-
-
-
-
UART1
Receive register DATA FULL
I2C interrupt
I2C
Yes
Yes
-
-
Reserved
Reserved
ADC1 end of conversion/analog
watchdog interrupt
22
ADC1
-
-
0x00 8060
23
24
TIM4
Flash
TIM4 update/overflow
EOP/WR_PG_DIS
-
-
-
-
0x00 8064
0x00 8068
0x00 806C to
0x00 807C
Reserved
1. Except PA1
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