Memory and register map
STM8S003F3 STM8S003K3
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
Status
Address
Block
Register Label
Register Name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B to
0x00 7F9F
Reserved area (5 byte)
1. Accessible by debug module only
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