STM8S003F3 STM8S003K3
Memory and register map
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
0x00 530C
0x00 530D
00 530E
TIM2_CR1
TIM2 control register 1
Reserved
0x00
Reserved
TIM2_IER
TIM2_SR1
TIM2 interrupt enable register
TIM2 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register 1
TIM2 capture/compare enable register 2
TIM2 counter high
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM2
TIM2 counter low
TIM2 prescaler register
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315
0x00 5316
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
TIM2 capture/compare register 3 low
0x00 5317 to
0x00 533F
Reserved area (43 byte)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
TIM4_CR1
TIM4 control register 1
Reserved
0x00
Reserved
TIM4_IER
TIM4_SR
TIM4 interrupt enable register
TIM4 status register
TIM4 event generation register
TIM4 counter
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 prescaler register
TIM4 auto-reload register
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