STM8S003F3 STM8S003K3
Memory and register map
Table 9. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
I2C_DR
I2C_SR1
I2C data register
I2C status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C_PECR
I2C packet error checking register
0x00 521F to
0x00 522F
Reserved area (17 byte)
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
UART1_SR
UART1_DR
UART1 status register
UART1 data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
UART1
0x00 523B to
0x00523F
Reserved area (21 byte)
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