STM8S003F3 STM8S003K3
Memory and register map
Table 9. General hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 501E to
0x00 5059
Reserved area (60 byte)
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH _FPR
FLASH _NFPR
Flash control register 1
Flash control register 2
0x00
0x00
0xFF
0x00
0xFF
Flash complementary control register 2
Flash protection register
Flash
Flash complementary protection register
Flash in-application programming status
register
0x00 505F
FLASH _IAPSR
0x00
0x00 5060 to
0x00 5061
Reserved area (2 byte)
Flash Program memory unprotection
register
0x00 5062
Flash
Flash
FLASH _PUKR
FLASH _DUKR
0x00
0x00
0x00 5063
0x00 5064
Reserved area (1 byte)
Data EEPROM unprotection register
0x00 5065 to
0x00 509F
Reserved area (59 byte)
0x00 50A0
0x00 50A1
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
ITC
RST
CLK
0x00 50A2 to
0x00 50B2
Reserved area (17 byte)
Reset status register
0x00 50B3
RST_SR
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 byte)
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
Reserved area (1 byte)
0x01
0x00
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
CLK_CCOR
CLK_PCKENR2
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