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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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I2C BUS INTERFACE  
2
I C BUS INTERFACE (Cont’d)  
INTERRUPT VECTOR REGISTER (I2CIVR)  
R249 - Read / Write  
Register Page: 20 (I2C_0) or 22 (I2C_1)  
Reset Value: Undefined  
(DMA between peripheral and Register file), this  
register has no meaning.  
See Section 10.8.6.1 for more details on the use  
of this register.  
7
0
Bit 0 = RPS Receiver DMA Memory Pointer Selec-  
tor.  
If memory has been selected for DMA transfer  
(I2CRDC.RF/MEM = 0) then:  
V7  
V6  
V5  
V4  
V3 EV2 EV1  
0
0: Select ISR register for Receiver DMA transfer  
address extension.  
1: Select DMASR register for Receiver DMA trans-  
fer address extension.  
Bits 7:3 = V[7:3] Interrupt Vector Base Address.  
User programmable interrupt vector bits. These  
are the five more significant bits of the interrupt  
vector base address. They must be set before en-  
abling the interrupt features.  
RECEIVER DMA TRANSACTION COUNTER  
REGISTER (I2CRDC)  
Bits 2:1 = EV[2:1] Encoded Interrupt Source.  
These Read-Only bits are set by hardware accord-  
ing to the interrupt source:  
R251 - Read / Write  
Register Page: 20 (I2C_0) or 22 (I2C_1)  
Reset Value: Undefined  
– 01: error condition detected  
– 10: data received  
7
0
– 11: peripheral ready to transmit  
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RF/MEM  
Bit 0 = Reserved.  
Bits 7:1 = RC[7:1] Receiver DMA Counter Pointer.  
I2CRDC contains the address of the pointer (in the  
Register File) of the DMA receiver transaction  
counter when the DMA between Peripheral and  
Memory Space is selected. Otherwise (DMA be-  
tween Peripheral and Register File), this register  
points to a pair of registers that are used as DMA  
Address register and DMA Transaction Counter.  
See Section 10.8.6.1 and Section 10.8.6.2 for  
more details on the use of this register.  
Forced by hardware to 0.  
RECEIVER DMA SOURCE ADDRESS POINTER  
REGISTER (I2CRDAP)  
R250 - Read / Write  
Register Page: 20 (I2C_0) or 22 (I2C_1)  
Reset Value: Undefined  
7
0
RA7 RA6 RA5 RA4 RA3 RA2 RA1  
RPS  
Bit 0 = RF/MEM Receiver Register File/ Memory  
Selector.  
0: DMA towards Memory  
Bits 7:1 = RA[7:1] Receiver DMA Address Pointer.  
I2CRDAP contains the address of the pointer (in  
the Register File) of the Receiver DMA data  
source when the DMA is selected between the  
peripheral and the Memory Space. Otherwise,  
1: DMA towards Register file  
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