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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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I2C BUS INTERFACE  
2
I C BUS INTERFACE (Cont’d)  
INTERRUPT MASK REGISTER (I2CIMR)  
R255 - Read / Write  
Register Page: 20 (I2C_0) or 22 (I2C_1)  
Reset Value: 00xx 0000 (x0h)  
interrupt request.  
Note: TEOBP can only be written to “0”.  
0: End of block not reached  
1: End of data block in DMA transmitter detected.  
7
0
Bit 3 = Reserved. This bit must be cleared.  
RXDM TXDM REOBP TEOBP  
0
IERRM IRXM ITXM  
Bit 2 = IERRM Error Condition interrupt mask bit.  
This bit enables/ disables the Error interrupt.  
0: Error interrupt disabled.  
Bit 7 = RXDM Receiver DMA Mask.  
0: DMA reception disable.  
1: DMA reception enable  
1: Error Interrupt enabled.  
RXDM is reset by hardware when the transaction  
counter value decrements to zero, that is when a  
Receiver End Of Block interrupt is issued.  
Bit 1 = IRXM Data Received interrupt mask bit.  
This bit enables/ disables the Data Received and  
Receive DMA End of Block interrupts.  
0: Interrupts disabled  
Bit 6 = TXDM Transmitter DMA Mask.  
0: DMA transmission disable.  
1: DMA transmission enable.  
TXDM is reset by hardware when the transaction  
counter value decrements to zero, that is when a  
Transmitter End Of Block interrupt is issued.  
1: Interrupts enabled  
Note: This bit has no effect on DMA transfer  
Bit 0 = ITXM Peripheral Ready To Transmit inter-  
rupt mask bit.  
This bit enables/ disables the Peripheral Ready To  
Transmit and Transmit DMA End of Block inter-  
rupts.  
Bit 5 = REOBP Receiver DMA End Of Block Flag.  
REOBP should be reset by software in order to  
avoid undesired interrupt routines, especially in in-  
itialization routine (after reset) and after entering  
the End Of Block interrupt routine.Writing “0” in  
this bit will cancel the interrupt request  
0: Interrupts disabled  
1: Interrupts enabled  
Note: This bit has no effect on DMA transfer.  
Note: REOBP can only be written to “0”.  
0: End of block not reached.  
1: End of data block in DMA receiver detected  
Bit 4 = TEOBP Transmitter DMA End Of Block TE-  
OBP should be reset by software in order to avoid  
undesired interrupt routines, especially in initializa-  
tion routine (after reset) and after entering the End  
Of Block interrupt routine.Writing “0” will cancel the  
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