I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Figure 127. I C BUS Protocol
SDA
SCL
ACK
9
MSB
1
2
8
START
STOP
CONDITION
CONDITION
VR02119B
2
Any transfer can be done using either the I C
registers directly or via the DMA.
The multimaster function is enabled with an auto-
matic switch from master mode to slave mode
2
when the interface loses the arbitration of the I C
If the transfer is to be done directly by accessing
the I2CDR, the interface waits (by holding the SCL
line low) for software to write in the Data Register
before transmission of a data byte, or to read the
Data Register after a data byte is received.
bus.
2
10.8.4.1 I C Slave Mode
As soon as a start condition is detected, the
address word is received from the SDA line and
sent to the shift register; then it is compared with
the address of the interface or the General Call
address (if selected by software).
If the transfer is to be done via DMA, the interface
sends a request for a DMA transfer. Then it waits
for the DMA to complete. The transfer between the
2
interface and the I C bus will begin on the next
Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
rising edge of the SCL clock.
■ Header (10-bit mode) or Address (both 10-bit
and 7-bit modes) not matched: the state
machine is reset and waits for another Start
condition.
■ Header matched (10-bit mode only): the
interface generates an acknowledge pulse if the
ACK bit of the control register (I2CCR) is set.
■ Address matched: the I2CSR1.ADSL bit is set
and an acknowledge bit is sent to the master if
the I2CCR.ACK bit is set. An interrupt request
occurs if the I2CCR.ITE bit is set. Then the SCL
line is held low until the microcontroller reads
the I2CSR1 register (see Figure 128 Transfer
sequencing EV1).
The SCL frequency (F ) generated in master
scl
mode is controlled by a programmable clock divid-
2
er. The speed of the I C interface may be selected
between Standard (0-100KHz) and Fast (100-
2
400KHz) I C modes.
2
10.8.4 I C State Machine
2
To enable the interface in I C mode the I2CCR.PE
bit must be set twice as the first write only acti-
vates the interface (only the PE bit is set); and the
bit7 of I2CCR register must be cleared.
2
The I C interface always operates in slave mode
(the M/SL bit is cleared) except when it initiates a
transmission or a receipt sequencing (master
mode).
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