I2C BUS INTERFACE
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10.8 I C BUS INTERFACE
10.8.1 Introduction
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The I C bus Interface serves as an interface be-
Interrupt Features:
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tween the microcontroller and the serial I C bus. It
■ Interrupt generation on error condition, on
provides both multimaster and slave functions with
both 7-bit and 10-bit address modes; it controls all
transmission request and on data received
■ Interrupt address vector for each interrupt
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I C bus-specific sequencing, protocol, arbitration,
source
timing and supports both standard (100KHz) and
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■ Pending bit and mask bit for each interrupt
fast I C modes (400KHz).
source
Using DMA, data can be transferred with minimum
use of CPU time.
■ Programmable interrupt priority respects the
other peripherals of the microcontroller
The peripheral uses two external lines to perform
the protocols: SDA, SCL.
■ Interrupt address vector programmable
DMA Features:
10.8.2 Main Features
■ Parallel-bus/I C protocol converter
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■ DMA both in transmission and in reception with
enabling bits
■ Multi-master capability
■ 7-bit/10-bit Addressing
■ DMA from/toward both Register File and
Memory
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■ Standard I C mode/Fast I C mode
■ Transmitter/Receiver flag
■ End Of Block interrupt sources with the related
pending bits
■ End-of-byte transmission flag
■ Transfer problem detection
■ Interrupt generation on error conditions
■ Interrupt generation on transfer request and on
data received
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I C Master Features:
■ Start bit detection flag
■ Clock generation
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■ I C bus busy flag
■ Arbitration Lost flag
■ End of byte transmission flag
■ Transmitter/Receiver flag
■ Stop/Start generation
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I C Slave Features:
■ Stop bit detection
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■ I C bus busy flag
■ Detection of misplaced start or stop condition
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■ Programmable I C Address detection (both 7-
bit and 10-bit mode)
■ General Call address programmable
■ Transfer problem detection
■ End of byte transmission flag
■ Transmitter/Receiver flag.
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STMICROELECTRONICS [ ST ]
