I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Figure 128. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
DataN
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
DataN
....
A
P
r
.
EV1 EV3
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV5
EV9
EV6 EV8
EV8
EV8
A
10-bit Master receiver:
Legend:
S
Header
A
Data1
A
DataN
P
r
.....
EV5
EV6
EV7
EV7
S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
is complete.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
is complete.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the
lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by
STOP=1, STOP=0 the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
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STMICROELECTRONICS [ ST ]
