Electrical characteristics
ST10F276E
23.8.2
Definition of internal timing
The internal operation of the ST10F276E is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate fCPU
.
This influence must be regarded when calculating the timings for the ST10F276E.
The example for PLL operation shown in Figure 52 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
Figure 52. Generation mechanisms for the CPU clock
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
