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NAND256R4A0AZA6F 参数 Datasheet PDF下载

NAND256R4A0AZA6F图片预览
型号: NAND256R4A0AZA6F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆, 256兆, 512兆, 1千兆( X8 / X16 ), 528字节/字264页, 1.8V / 3V , NAND闪存 [128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 57 页 / 916 K
品牌: STMICROELECTRONICS [ ST ]
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A  
Figure 21. Garbage Collection  
Old Area  
New Area (After GC)  
Valid  
Page  
Invalid  
Page  
Free  
Page  
(Erased)  
AI07599B  
Garbage Collection  
Error Correction Code  
When a data page needs to be modified, it is faster  
to write to the first available page, and the previous  
page is marked as invalid. After several updates it  
is necessary to remove invalid pages to free some  
memory space.  
To free this memory space and allow further pro-  
gram operations it is recommended to implement  
a Garbage Collection algorithm. In a Garbage Col-  
lection software the valid pages are copied into a  
free area and the block containing the invalid pag-  
es is erased (see Figure 21.).  
An Error Correction Code (ECC) can be imple-  
mented in the Nand Flash memories to identify  
and correct errors in the data.  
For every 2048 bits in the device it is recommend-  
ed to implement 22 bits of ECC (16 bits for line par-  
ity plus 6 bits for column parity).  
An ECC model is available in VHDL or Verilog.  
Contact the nearest ST Microelectronics sales of-  
fice for more details.  
Figure 22. Error Detection  
Wear-leveling Algorithm  
For write-intensive applications, it is recommend-  
ed to implement a Wear-leveling Algorithm to  
monitor and spread the number of write cycles per  
block.  
New ECC generated  
during read  
In memories that do not use a Wear-Leveling Algo-  
rithm not all blocks get used at the same rate.  
Blocks with long-lived data do not endure as many  
write cycles as the blocks with frequently-changed  
data.  
The Wear-leveling Algorithm ensures that equal  
use is made of all the available write cycles for  
each block. There are two wear-leveling levels:  
XOR previous ECC  
with new ECC  
NO  
NO  
>1 bit  
All results  
= zero?  
= zero?  
YES  
YES  
First Level Wear-leveling, new data is  
programmed to the free blocks that have had  
the fewest write cycles  
Second Level Wear-leveling, long-lived data is  
copied to another block so that the original  
block can be used for more frequently-  
changed data.  
22 bit data = 0  
11 bit data = 1  
1 bit data = 1  
ECC Error  
Correctable  
Error  
No Error  
ai08332  
The Second Level Wear-leveling is triggered when  
the difference between the maximum and the min-  
imum number of write cycles per block reaches a  
specific threshold.  
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