L7250
1.4 Inverted clock serial port timing Table
Symbol
Tcc
Parameter
Min
30
13
13
5
Max
Unit
ns
Serial clock period
Tch
Serial clock high time
ns
Tcl
Serial clock low time
ns
Tcds
Tcdh
Tedh
Tvld
Serial data setup time to clock falling edge (write mode)
Serial clock falling edge to serial data hold time (write mode)
Serial clock falling edge to serial data hold time (read mode)
ns
4
ns
5
ns
Serial clock rising edge to SDATA stable time (read mode)
Cload=5pF (see Note2)
Cload=50pF (see Note2)
11
15
ns
ns
Tel
Teh
Serial Enable low time
490
30
17
17
0
ns
ns
ns
ns
ns
Serial Enable high time
Tefcr
Tcrer
Tdly
Serial Enable falling edge to serial clock rising edge
Serial clock rising edge to Serial enable rising edge
SDATA turn around delay time
Note 1: All specifications with respect to 50% of signal switching thresholds
Note 2: In reading mode the clock frequency is limited by this parameter;
in fact the min ‘serial clock high time’ is defined by (Tvld+Tasu)
where Tasu = min ASIC setup time
15/46
STMICROELECTRONICS [ ST ]
