L7250
Figure 2. Inverted clock serial port timing diagram (bit 7, Reg05H = 1)
Note1: During writing process L7250 latches the data on the SCLK rising edge (the ASIC is writing on the SCLK
falling edge)
Note2: During reading process L7250 takes the bus control on the next SCLK falling edge after the 8th SCLKris-
ing edge
The L7250 write the data on the SCLK rising edge and it is expecting the ASIC to latches the data on the SCLK
falling edge
Note3: The ID number for the L7250 is ID1=ID2=ID3=1
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