1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Block-Erase
The Block-Erase instruction clears all bits in the selected block to ‘1’. Block sizes can be 8 KByte, 32
KByte or 64 KByte depending on address, see Figure 3, Memory Map, for details. A Block-Erase
instruction applied to a protected memory area will be ignored. Prior to any write operation, execute
the WREN instruction. Keep CE# active low for the duration of any command sequence.
To execute a Block-Erase operation, the host drives CE# low then sends the Block-Erase command
cycle (D8H), three address cycles, then drives CE# high. Each cycle is two nibbles, or clocks, long,
most significant nibble first. Address bits AMS-A13 determine the block address; the remaining address
bits can be VIL or VIH. For 32 KByte blocks, A14:A13 can be VIL or VIH; for 64 KByte blocks, A15:A13 can
be VIL or VIH. Poll the BUSY bit in the Status register or wait TBE for the completion of the internal, self-
timed, Block-Erase operation See Figure 16 for the Block-Erase sequence.
CE#
MODE 3
MODE 0
0
1
2
4
6
SCK
SIO(3:0)
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
1409 F08.0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
C[1:0] = D8H
Figure 16:Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to ‘1.’ The Chip-Erase instruction is ignored if
any of the memory area is protected. Prior to any write operation, execute the the WREN instruction.
To execute a Chip-Erase operation, the host drives CE# low, sends the Chip-Erase command cycle
(C7H), then drives CE# high. A cycle is two nibbles, or clocks, long, most significant nibble first. Poll the
BUSY bit in the Status register or wait TCE for the completion of the internal, self-timed, Chip-Erase
operation. See Figure 17 for the Chip Erase sequence.
CE#
MODE 3
MODE 0
0
1
SCK
SIO(3:0)
C1 C0
1409 F09.0
Note: C[1:0] = C7H
Figure 17:Chip-Erase Sequence
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