1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
JEDEC-ID Read (SPI Protocol)
Using traditional SPI protocol, the JEDEC-ID Read instruction identifies the device as SST26WF032
and the manufacturer as SST. To execute a JECEC-ID operation the host drives CE# low then sends
the JEDEC-ID command cycle (9FH). For SPI modes, each cycle is eight bits (clocks) long, most sig-
nificant bit first.
Immediately following the command cycle the device outputs data on the falling edge of the SCK sig-
nal. The data output stream is continuous until terminated by a low-to-high transition on CE#. The
device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure
13 for instruction sequence.
Table 6: Device ID Data Output
Device ID
Manufacturer ID
(Byte 1)
Device Type
(Byte 2)
Device ID
(Byte 3)
Product
SST26WF032
BFH
26H
22H
T6.1 1409
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK
SI
9F
HIGH IMPEDANCE
26
Device ID
BF
SO
MSB
MSB
1409 F38.0
Note: SIO2 and SIO3 must be driven VIH
Figure 13:JEDEC-ID Sequence (SPI Mode)
Quad J-ID Read (SQI Protocol)
The Quad J-ID Read instruction identifies the device as SST26WF032 and manufacturer as SST. To
execute a Quad J-ID operation the host drives CE# low and then sends the Quad J-ID command cycle
(AFH). Each cycle is two nibbles (clocks) long, most significant nibble first.
Immediately following the command cycle the device outputs data on the falling edge of the SCK sig-
nal. The data output stream is continuous until terminated by a low-to-high transition of CE#. The
device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure
14 for instruction sequence.
©2010 Silicon Storage Technology, Inc.
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