1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Reset Quad I/O (RSTQIO)
The Reset Quad I/O instruction, FFH, resets the device to 1-bit SPI protocol operation. To execute a
Reset Quad I/O operation, the host drives CE# low, sends the Reset Quad I/O command cycle (FFH)
then, drives CE# high. The device accepts either SPI (8 clocks) or SQI (2 clocks) command cycles. For
SPI, SIO[3:1] are don’t care for this command, but should be driven to VIH or VIL.
High-Speed Read (80 MHz)
The High-Speed Read instruction, 0BH, is supported in both SPI bus protocol and SQI protocol. On
power-up, the device is set to use SPI.
Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and
a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. SIO2 and
SIO3 must be driven VIH for the duration of the Read cycle. See Figure 10 for the High-Speed Read
sequence for SPI bus protocol.
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
0B
ADD.
ADD.
ADD.
X
SI/SIO0
N
N+1
N+2
N+3
N+4
HIGH IMPEDANCE
SO/SIO1
D
D
OUT
D
OUT
D
OUT
D
OUT
OUT
MSB
1409 F31.0
Note: SIO2 and SIO3 must be driven VIH
Figure 10:High-Speed Read Sequence (SPI)
In SQI protocol, the host drives CE# low then send the Read command cycle command, 0BH, followed by three
address cycles and two dummy cycles. Each cycle is two nibbles (clocks) long, most significant nibble first.
After the dummy cycles, the 1.8V Serial Quad I/O (SQI) Flash Memory outputs data on the falling
edge of the SCK signal starting from the specified address location. The device continually streams
data output through all addresses until terminated by a low-to-high transition on CE#. The internal
address pointer automatically increments until the highest memory address is reached, at which point
the address pointer returns to address location 000000H.
During this operation, blocks that are Read-locked will output data 00H.
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
18
19
20
21
MODE 3
MODE 0
SCK
MSN
LSN
L0
C0 C1 A5 A4 A3 A2
Command Address
A0
X
X
X
X
H0
H8 L8 H9 L9
SIO(3:0)
A1
Dummy
Data Byte 0
Data Byte 8 Data Byte 9
1409 F44.1
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
Figure 11:High-Speed Read and Read Burst Sequence (SQI)
©2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
15
SST [ SILICON STORAGE TECHNOLOGY, INC ]
