1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Program Security ID
The Program Security ID instruction programs one to 24 Bytes of data in the user-programmable,
Security ID space. The device ignores a Program Security ID instruction pointing to an invalid or pro-
tected address, see Table 7. Prior to the program operation, execute WREN.
To execute a Program SID operation, the host drives CE# low, sends the Program Security ID com-
mand cycle (A5H), one address cycle, the data to be programmed, then drives CE# high. The pro-
grammed data must be between 1 to 24 Bytes and in whole Byte increments; sending an odd number
of nibbles will cause the last nibble to be ignored. Each cycle is two nibbles long, most significant nib-
ble first. To determine the completion of the internal, self-timed Program SID operation, poll the BUSY
bit in the software status register, or wait TPSID for the completion of the internal self-timed Program
Security ID operation.
Table 7: Program Security ID
Program Security ID
Pre-Programmed at factory
User Programmable
Address Range
00H – 07H
08H – 1FH
T7.0 1409
Lockout Security ID
The Lockout Security ID instruction prevents any future changes to the Security ID. To execute a Lock-
out SID, the host drives CE# low, sends the Lockout Security ID command cycle (85H), then drives
CE# high. A cycle is two nibbles long, most significant nibble first. The user map polls the BUSY bit in
the software status register or waits TPSID for the completion of he Lockout Security ID operation.
Read-Status Register (RDSR)
The Read-Status register (RDSR) command outputs the contents of the Status register. The Status register
may be read at any time even during a Write operation. When a Write is in progress, check the BUSY bit
before sending any new commands to assure that the new commands are properly received by the device.
To execute a Read-Status-Register operation the host drives CE# low, then sends the Read-Status-
Register command cycle (05H). Each cycle is two nibbles long, most significant nibble first. Immedi-
ately after the command cycle, the device outputs data on the falling edge of the SCK signal. The data
output stream continues until terminated by a low-to-high transition on CE#. See Figure 20 for the
RDSR instruction sequence.
CE#
MODE 3
0
2
4
6
8
N
SCK MODE 0
SIO(3:0)
C1 C0 H0 L0 H0 L0 H0 L0
H0 L0
MSN LSN
Status Byte Status Byte Status Byte
Status Byte
1409 F11.0
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble
C[1:0] = 05H
Figure 20:Read-Status-Register (RDSR) Sequence
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