1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
CE#
SCK
MODE 3
MODE 0
0
2
4
6
8
10
12
N
SIO(3:0)
C1 C0 H0 L0 H1 L1 H2 L2 H0 L0 H1 L4 H2 L2
HN LN
MSN LSN
BFH
26H
Device ID
BFH
26H
Device ID
N
1409 F39.0
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble
C[1:0]=AFH
Figure 14:Quad J-ID Read Sequence
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to ‘1,’ but it does not change
a protected memory area. Prior to any write operation, the Write-Enable (WREN) instruction must be
executed.
To execute a Sector-Erase operation, the host drives CE# low, then sends the Sector Erase command
cycle (20H) and three address cycles, and then drives CE# high. Each cycle is two nibbles, or clocks,
long, most significant nibble first. Address bits [AMS:A12] (AMS = Most Significant Address) determine
the sector address (SAX); the remaining address bits can be VIL or VIH. Poll the BUSY bit in the Status
register or wait TSE for the completion of the internal, self-timed, Sector-Erase operation. See Figure
15 for the Sector-Erase sequence.
CE#
MODE 3
MODE 0
0
1
2
4
6
SCK
SIO(3:0)
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
1409 F07.0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
C[1:0] = 20H
Figure 15:4 KByte Sector-Erase Sequence
©2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
18
SST [ SILICON STORAGE TECHNOLOGY, INC ]
