1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Write-Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to ‘1,’
allowing Write operations to occur. The WREN instruction must be executed prior to any of the follow-
ing operations: Sector Erase, Block Erase, Chip Erase, Page Program, Program Security ID, Lockout
Security ID, Write Block-Protection Register and Lockdown Block-Protection Register. To execute a
Write Enable the host drives CE# low then sends the Write Enable command cycle (06H) then drives
CE# high. A cycle is two nibbles (clocks) long, most significant nibble first. See Figure 21 for the WREN
instruction sequence.
CE#
MODE 3
MODE 0
0
1
SCK
SIO(3:0)
C1 C0
1409 F12.0
Note: C[1:0] = 06H
Figure 21:Write-Enable Sequence
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction sets the Write-Enable-Latch bit in the Status Register to ‘0,’ pre-
venting Write execution without a prior WREN instruction. To execute a Write-Disable, the host drives
CE# low, sends the Write Disable command cycle (04H), then drives CE# high. A cycle is two nibbles
long, most significant nibble first.
CE#
MODE 3
MODE 0
0
1
SCK
SIO(3:0)
C1 C0
1409 F33.0
Note: C[1:0] = 04H
Figure 22:Write-Disable (WRDI) Sequence
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