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SST26WF032-80-4I-S2AE 参数 Datasheet PDF下载

SST26WF032-80-4I-S2AE图片预览
型号: SST26WF032-80-4I-S2AE
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V串行四I / O( SQI )快闪记忆体 [1.8V Serial Quad I/O (SQI) Flash Memory]
分类和应用:
文件页数/大小: 36 页 / 1340 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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1.8V Serial Quad I/O (SQI) Flash Memory  
SST26WF032  
Advance Information  
Set Burst  
The Set Burst command specifies the number of bytes to be output during a Read Burst command  
before the device wraps around. To set the burst length the host drives CE# low, sends the Set Burst  
command cycle (C0H) and one data cycle, then drives CE# high. A cycle is two nibbles, or two clocks,  
long, most significant nibble first. After power-up or reset, the burst length is set to eight Bytes (00H).  
See Table 4 for burst length data and Figure 12 for the sequence.  
Table 4: Burst Length Data  
Burst Length  
8 Bytes  
High Nibble (H0)  
Low Nibble (L0)  
0h  
0h  
0h  
0h  
0h  
1h  
2h  
3h  
16 Bytes  
32 Bytes  
64 Bytes  
T4.0 1409  
CE#  
SCK  
MODE 3  
MODE 0  
0
1
2
3
SIO(3:0)  
C1 C0 H0 L0  
MSN LSN  
1409 F32.0  
Note: MSN = Most Significant Nibble,  
LSN = Least Significant Nibble  
Figure 12:Set Burst Length Sequence  
Read Burst  
To execute a Read Burst operation the host drives CE# low, then sends the Read Burst command  
cycle (0CH), followed by three address cycles, and then one dummy cycle. Each cycle is two nibbles  
(clocks) long, most significant nibble first.  
After the dummy cycle, the device outputs data on the falling edge of the SCK signal starting from the  
specified address location. The data output stream is continuous through all addresses until termi-  
nated by a low-to-high transition on CE#.  
During Read Burst, the internal address pointer automatically increments until the last byte of the burst  
is reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the burst  
length, see Table 5. For example, if the burst length is eight Bytes, and the start address is 06h, the  
burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern would repeat  
until the command was terminated by a low-to-high transition on CE#.  
During this operation, blocks that are Read-locked will output data 00H.  
Table 5: Burst Address Ranges  
Burst Length  
8 Bytes  
Burst Address Ranges  
00-07H, 08-0FH, 10-17H, 18-1FH...  
00-0FH, 10-1FH, 20-2FH, 30-3FH...  
00-1FH, 20-3FH, 40-5FH, 60-7FH...  
00-3FH, 40-7FH, 80-BFH, C0-FFH  
16 Bytes  
32 Bytes  
64 Bytes  
T5.0 1409  
©2010 Silicon Storage Technology, Inc.  
S71409-01-000  
01/10  
16  
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