1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Read (25 MHz)
The Read instruction, 03H, is supported in SPI bus protocol only with clock frequencies up to 25 MHz.
This command is not supported in SQI bus protocol. The device outputs the data starting from the
specified address location, then continuously streams the data output through all addresses until ter-
minated by a low-to-high transition on CE#. The internal address pointer will automatically increment
until the highest memory address is reached. Once the highest memory address is reached, the
address pointer will automatically return to the beginning (wrap-around) of the address space.
Initiate the Read instruction by executing an 8-bit command, 03H, followed by address bits A23:A0.
CE# must remain active low for the duration of the Read cycle. SIO2 and SIO3 must be driven VIH for
the duration of the Read cycle. See Figure 8 for Read Sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
70
MODE 0
SCK
SI
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
MSB
N
OUT
N+1
N+2
N+3
N+4
D
OUT
D
D
D
OUT
D
OUT
OUT
SO
MSB
1409 F29.0
Note: SIO2 and SIO3 must be driven VIH
Figure 8: Read Sequence (SPI)
Enable Quad I/O (EQIO)
The Enable Quad I/O (EQIO) instruction, 38H, enables the flash device for SQI bus operation. upon
completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a
power cycle or a “Reset Quad I/O instruction” is executed. See Figure 9.
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
SCK
SIO0
38
SIO[3:1]
1409 F43.0
Figure 9: Enable Quad I/O Sequence
©2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
14
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