2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
1
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
17-0
2
T
AH
T
DH
T
CP
CE#
3
T
T
AS
DS
T
CPH
OE#
4
T
CH
WE#
5
T
CS
DQ
7-0
AA
55
A0
DATA
6
SW0
SW1
SW2
BYTE
(ADDR/DATA)
326 ILL F05.3
7
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
8
9
10
11
12
13
14
15
16
ADDRESS A
17-0
T
CE
CE#
T
OES
T
OEH
OE#
WE#
T
OE
DQ
7
D
D#
D#
D
326 ILL F06.0
FIGURE 6: DATA# POLLING TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc.
326-10 12/98
11