2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
T
1
SCE
SIX-BYTE CODE FOR CHIP ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
17-0
CE#
2
3
OE#
4
T
WP
WE#
5
DQ
7-0
AA
55
80
AA
55
10
6
SW0
SW1
SW2
SW3
SW4
SW5
326 ILL F17.1
7
Note: The device also supports CE# controlled chip erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 10)
8
FIGURE 9: WE# CONTROLLED CHIP ERASE TIMING DIAGRAM
9
Three-byte sequence for
Software ID Entry
10
11
12
13
14
15
16
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
55
SW1
T
AA
DQ
7-0
90
BF
B6
SW0
SW2
326 ILL F09.3
FIGURE 10: SOFTWARE ID ENTRY AND READ
© 1998 Silicon Storage Technology, Inc.
326-10 12/98
13
SST [ SILICON STORAGE TECHNOLOGY, INC ]
