2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
ADDRESS A
17-0
T
CE
CE#
T
OES
T
T
OE
OEH
OE#
WE#
DQ
6
(1)
TWO READ CYCLES
WITH SAME OUTPUTS
NOTE: (1) TOGLE BIT OUTPUT IS ALWAYS HIGH FIRST.
326 ILL F07.0
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR ERASE
5555 5555 2AAA
5555
2AAA
SA
X
ADDRESS A
17-0
CE#
OE#
T
WP
WE#
DQ
7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
326 ILL F08.4
Note: The device also supports CE# controlled sector erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 10)
SAX = Sector Address
FIGURE 8: WE# CONTROLLED SECTOR ERASE TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc.
326-10 12/98
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
