2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
T
T
AA
RC
ADDRESS A
17-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
326 ILL F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
17-0
T
AH
T
DH
T
WP
WE#
OE#
CE#
T
T
AS
DS
T
WPH
T
CH
T
CS
DQ
7-0
AA
55
A0
DATA
SW0
SW1
SW2
BYTE
(ADDR/DATA)
326 ILL F04.3
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
© 1998 Silicon Storage Technology, Inc.
326-10 12/98
10