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CY28446 参数 Datasheet PDF下载

CY28446图片预览
型号: CY28446
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢ Calistoga的芯片组 [Clock Generator for Intel㈢ Calistoga Chipset]
分类和应用: 时钟发生器
文件页数/大小: 19 页 / 180 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28446  
Byte 8: Control Register 7  
Bit  
7
@Pup  
Name  
Description  
0
1
Reserved  
SRC[T/C]10  
Reserved set to 0  
6
SRC[T/C]10 Output Enable  
0 = Disable (Tri-state), 1 = Enable  
5
4
1
1
SRC[T/C]9  
SRC[T/C]8  
SRC[T/C]9 Output Enable  
0 = Disable (Tri-state), 1 = Enable  
SRC[T/C]8 Output Enable  
0 = Disable (Tri-state), 1 = Enable  
3
2
0
0
Reserved  
SRC10  
Reserved set to 0  
Allow control of SRC[T/C]10 with assertion of OEA#  
0 = Free running, 1 = Stopped with OEA#  
1
0
0
0
SRC9  
SRC8  
Allow control of SRC[T/C]9 with assertion of OEB#  
0 = Free running, 1 = Stopped with OEB#  
Allow control of SRC[T/C]8 with assertion of OEA#  
0 = Free running, 1 = Stopped with OEA#  
Byte 9: Control Register 8  
Bit  
@Pup  
Name  
Description  
7
0
PCI3  
33-MHz Output drive strength  
0 = Low, 1 = High  
6
5
4
3
0
0
0
0
PCI2  
PCI1  
33-MHz Output drive strength  
0 = Low, 1 = High  
33-MHz Output drive strength  
0 = Low, 1 = High  
PCI0  
33-MHz Output drive strength  
0 = Low, 1 = High  
PCIF0  
33-MHz Output drive strength  
0 = Low, 1 = High  
2
1
0
1
1
1
Reserved  
Reserved  
Reserved  
Reserved set to 1  
Reserved set to 1  
Reserved set to 1  
.
Crystal Recommendations  
Frequency  
(Fund)  
Drive  
(max.)  
Shunt Cap Motional  
(max.)  
Tolerance  
(max.)  
Stability  
(max.)  
Aging  
(max.)  
Cut  
Loading Load Cap  
Parallel 20 pF  
(max.)  
14.31818 MHz  
AT  
0.1 mW  
5 pF  
0.016 pF  
35 ppm  
30 ppm  
5 ppm  
The CY28446 requires a Parallel Resonance Crystal. Substi-  
tuting a series resonance crystal causes the CY28446 to  
operate at the wrong frequency and violate the ppm specifi-  
cation. For most applications there is a 300-ppm frequency  
shift between series and parallel crystals due to incorrect  
loading  
.
Crystal Loading  
Crystal loading plays a critical role in achieving low ppm perfor-  
mance. To realize low ppm performance, use the total capac-  
itance the crystal sees to calculate the appropriate capacitive  
loading (CL).  
Figure 1. Crystal Capacitive Clarification  
Figure 1 shows a typical crystal configuration using the two  
trim capacitors. It is important that the trim capacitors are in  
series with the crystal. It is not true that load capacitors are in  
parallel with the crystal and are approximately equal to the  
load capacitance of the crystal.  
Calculating Load Capacitors  
In addition to the standard external trim capacitors, consider  
the trace capacitance and pin capacitance to calculate the  
crystal loading correctly. Again, the capacitance on each side  
Rev 1.0,November 20, 2006  
Page 8 of 19