欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY28446 参数 Datasheet PDF下载

CY28446图片预览
型号: CY28446
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢ Calistoga的芯片组 [Clock Generator for Intel㈢ Calistoga Chipset]
分类和应用: 时钟发生器
文件页数/大小: 19 页 / 180 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28446的Datasheet PDF文件第5页浏览型号CY28446的Datasheet PDF文件第6页浏览型号CY28446的Datasheet PDF文件第7页浏览型号CY28446的Datasheet PDF文件第8页浏览型号CY28446的Datasheet PDF文件第10页浏览型号CY28446的Datasheet PDF文件第11页浏览型号CY28446的Datasheet PDF文件第12页浏览型号CY28446的Datasheet PDF文件第13页  
CY28446  
is in series with the crystal. The total capacitance on both side  
is twice the specified crystal load capacitance (CL). Trim  
capacitors are calculated to provide equal capacitive loading  
on both sides.  
CL....................................................Crystal load capacitance  
CLe......................................... Actual loading seen by crystal  
using standard value trim capacitors  
Ce..................................................... External trim capacitors  
Cs..............................................Stray capacitance (terraced)  
Ci ...........................................................Internal capacitance  
(lead frame, bond wires etc.)  
Clock Chip  
Ci2  
Ci1  
Pin  
3 to 6p  
OE# Description  
The OE# signals are active LOW inputs used for clean  
enabling and disabling selected SRC outputs. The outputs  
controlled by OE[A,B]# are determined by the settings in  
register byte 3 and byte 8. OE[0,1,3,6]# controls SRC[0,1,3,6],  
respectively. The OE# signal is a debounced signal and its  
state must remain unchanged during two consecutive rising  
edges of SRCC to be recognized as a valid assertion or  
deassertion. (The assertion and deassertion of this signal is  
absolutely asynchronous.)  
X2  
X1  
Cs2  
Cs1  
Trace  
2.8 pF  
XTAL  
Ce1  
Ce2  
Trim  
33 pF  
OE# Assertion (OE# -> LOW)  
Figure 2. Crystal Loading Example  
All differential stopped outputs resume normal operation in a  
glitch-free manner. The maximum latency from the assertion  
to active outputs is between 2 and 6 SRC clock periods (2  
Use the following formulas to calculate the trim capacitor  
values for Ce1 and Ce2.  
clocks are shown) with all SRC outputs resuming simulta-  
neously. All stopped SRC outputs must be driven HIGH within  
10 ns of OE# deassertion to a voltage er than 200 mV.  
Load Capacitance (each side)  
OE# Deassertion (OE# -> HIGH)  
Ce = 2 * CL – (Cs + Ci)  
The impact of deasserting the OE# pins is that all SRC outputs  
that are set in the control registers to stoppable via deassertion  
of OE# are stopped after their next transition. The final state  
of all stopped SRC clocks is Low/low.  
Total Capacitance (as seen by the crystal)  
1
CLe  
=
1
Ce2 + Cs2 + Ci2  
1
Ce1 + Cs1 + Ci1  
(
)
+
OE#  
SRCT(free running)  
SRCC(free running)  
SRCT(stoppable)  
SRCT(stoppable)  
Figure 3. OE# Deassertion/Assertion Waveform  
Rev 1.0,November 20, 2006  
Page 9 of 19